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PRTR5V0U2F; PRTR5V0U2K
Ultra low capacitance double rail-to-rail ESD protection
Rev. 02 -- 19 February 2009 Product data sheet
1. Product profile
1.1 General description
Ultra low capacitance double rail-to-rail ElectroStatic Discharge (ESD) protection devices in leadless ultra small Surface-Mounted Device (SMD) plastic packages. The devices are designed to protect two Hi-Speed data lines or high-frequency signal lines from the damage caused by ESD and other transients. PRTR5V0U2F and PRTR5V0U2K integrate two ultra low capacitance rail-to-rail ESD protection channels and one additional ESD protection diode each to ensure signal line protection even if no supply voltage is available.
Table 1. Product overview Package NXP PRTR5V0U2F PRTR5V0U2K SOT886 SOT891 JEDEC MO-252 leadless ultra small leadless ultra small Package configuration
Type number
1.2 Features
I I I I I I I I ESD protection of two Hi-Speed data lines or high-frequency signal lines Ultra low input/output to ground capacitance: C(I/O-GND) = 1 pF ESD protection up to 8 kV IEC 61000-4-2, level 4 (ESD) Very low clamping voltage due to an integrated additional ESD protection diode Very low reverse current AEC-Q101 qualified Leadless ultra small SMD plastic packages
1.3 Applications
I I I I I I I USB 2.0 interfaces Digital Video Interface (DVI) / High Definition Multimedia Interface (HDMI) interfaces Mobile and cordless phones Personal Digital Assistants (PDA) Digital cameras Wide Area Network (WAN) / Local Area Network (LAN) systems PCs, notebooks, printers and other PC peripherals
NXP Semiconductors
PRTR5V0U2F; PRTR5V0U2K
Ultra low capacitance double rail-to-rail ESD protection
1.4 Quick reference data
Table 2. Quick reference data Tamb = 25 C unless otherwise specified. Symbol Per channel C(I/O-GND) C(I/O-I/O) Zener diode VRWM Csup
[1] [2] [3]
Parameter input/output to ground capacitance input/output to input/output capacitance reverse standoff voltage supply pin to ground capacitance
Conditions f = 1 MHz; V(I/O-GND) = 0 V f = 1 MHz; V(I/O-I/O) = 0 V
[1]
Min -
Typ 1.0 0.6
Max 1.5 -
Unit pF pF
[2]
[3]
-
16
5.5 -
V pF
f = 1 MHz; VCC = 0 V
[3]
Measured from pin 1, 3, 4 or 6 to ground. Measured from pin 1 or 6 to pin 3 or 4. Measured from pin 5 to ground.
2. Pinning information
Table 3. Pin 1 2 3 4 5 6 Pinning Description input/output 1 ground input/output 2 input/output 2 supply voltage input/output 1
6 5 bottom view 4 3
006aab349
Symbol I/O1 GND I/O2 I/O2 VCC I/O1
Simplified outline
Graphic symbol
PRTR5V0U2F (SOT886)
1 2 3 1 6
2
5
4
PRTR5V0U2K (SOT891) 1 2 3 4 5 6 I/O1 GND I/O2 I/O2 VCC I/O1 input/output 1 ground input/output 2 input/output 2 supply voltage input/output 1
6 5 4 bottom view 3
006aab349
1
2
3 1 6
2
5
4
PRTR5V0U2F_PRTR5V0U2K_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 19 February 2009
2 of 12
NXP Semiconductors
PRTR5V0U2F; PRTR5V0U2K
Ultra low capacitance double rail-to-rail ESD protection
3. Ordering information
Table 4. Ordering information Package Name PRTR5V0U2F PRTR5V0U2K XSON6 XSON6 Description plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm Version SOT886 SOT891 Type number
4. Marking
Table 5. Marking codes Marking code PF PK Type number PRTR5V0U2F PRTR5V0U2K
5. Limiting values
Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Per device Tamb Tstg ambient temperature storage temperature -40 -55 +85 +125 C C Parameter Conditions Min Max Unit
Table 7. ESD maximum ratings Tamb = 25 C unless otherwise specified. Symbol VESD Parameter electrostatic discharge voltage Conditions IEC 61000-4-2 (contact discharge) MIL-STD-883 (human body model)
[1] [2] Device stressed with ten non-repetitive ESD pulses. Measured from pin 1, 3, 4 or 6 to pin 2 or 5.
[1][2]
Min -
Max 8 10
Unit kV kV
Per channel
[2]
PRTR5V0U2F_PRTR5V0U2K_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 19 February 2009
3 of 12
NXP Semiconductors
PRTR5V0U2F; PRTR5V0U2K
Ultra low capacitance double rail-to-rail ESD protection
ESD standards compliance Conditions > 8 kV (contact) > 4 kV
Table 8. Standard
Per channel IEC 61000-4-2; level 4 (ESD) MIL-STD-883; class 3 (human body model)
001aaa631
IPP 100 % 90 %
10 % tr = 0.7 ns to 1 ns 30 ns 60 ns t
Fig 1.
ESD pulse waveform according to IEC 61000-4-2
PRTR5V0U2F_PRTR5V0U2K_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 19 February 2009
4 of 12
NXP Semiconductors
PRTR5V0U2F; PRTR5V0U2K
Ultra low capacitance double rail-to-rail ESD protection
6. Characteristics
Table 9. Characteristics Tamb = 25 C unless otherwise specified. Symbol Per channel IR C(I/O-GND) C(I/O-I/O) VF Zener diode VRWM VBR Csup
[1] [2] [3] [4]
Parameter reverse current input/output to ground capacitance input/output to input/output capacitance forward voltage reverse standoff voltage breakdown voltage supply pin to ground capacitance
Conditions VR = 5 V f = 1 MHz; V(I/O-GND) = 0 V f = 1 MHz; V(I/O-I/O) = 0 V IF = 1 mA
[1] [1]
Min 6 -
Typ <1 1.0 0.6 0.7 16
Max 100 1.5 5.5 9 -
Unit nA pF pF V V V pF
[2]
[3]
[4] [4]
f = 1 MHz; VCC = 0 V
[4]
Measured from pin 1, 3, 4 or 6 to ground. Measured from pin 1 or 6 to pin 3 or 4. Measured from pin 1, 3, 4 or 6 to pin 5. Measured from pin 5 to ground.
2.0 C(I/O-GND) (pF) 1.6
006aaa483
1.0 C(I/O-I/O) (pF) 0.8
006aaa484
1.2
0.6
0.8
0.4
0.4
0.2
0 0 1 2 3 5 V(I/O-GND) (V) 4
0 0 1 2 3 4 5 V(I/O-I/O) (V)
f = 1 MHz; Tamb = 25 C
f = 1 MHz; Tamb = 25 C
Fig 2.
Input/output to ground capacitance as a function of input/output to ground voltage; typical values
Fig 3.
Input/output to ground capacitance as a function of input/output to input/output voltage; typical values
PRTR5V0U2F_PRTR5V0U2K_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 19 February 2009
5 of 12
NXP Semiconductors
PRTR5V0U2F; PRTR5V0U2K
Ultra low capacitance double rail-to-rail ESD protection
ESD TESTER RZ CZ
450
RG 223/U 50 coax
4 GHz DIGITAL OSCILLOSCOPE 10x ATTENUATOR
50
IEC 61000-4-2 network CZ = 150 pF; RZ = 330
DUT Device Under Test
vertical scale = 200 V/div horizontal scale = 50 ns/div
vertical scale = 10 V/div horizontal scale = 50 ns/div
GND
GND
unclamped +1 kV ESD voltage waveform (IEC 61000-4-2 network)
clamped +1 kV ESD voltage waveform (IEC 61000-4-2 network)
vertical scale = 10 V/div horizontal scale = 50 ns/div GND
GND
vertical scale = 200 V/div horizontal scale = 50 ns/div unclamped -1 kV ESD voltage waveform (IEC 61000-4-2 network) clamped -1 kV ESD voltage waveform (IEC 61000-4-2 network)
006aab112
Fig 4.
ESD clamping test setup and waveforms
PRTR5V0U2F_PRTR5V0U2K_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 19 February 2009
6 of 12
NXP Semiconductors
PRTR5V0U2F; PRTR5V0U2K
Ultra low capacitance double rail-to-rail ESD protection
7. Application information
Handling data rates up to 480 Mbit/s, USB 2.0 interfaces require ESD protection devices with an extremely low line capacitance in order to avoid signal distortion. With a capacitance of only 1 pF, the PRTR5V0U2F and the PRTR5V0U2K offer IEC 61000-4-2, level 4 compliant ESD protection. PRTR5V0U2F and PRTR5V0U2K integrate two pairs of ultra low capacitance rail-to-rail ESD protection channels and one additional ESD protection diode each. The additional ESD protection diode connected between ground and VCC prevents charging of the supply.
USB controller common mode choke D+ D- VBUS
protected IC/device VBUS D+ D- GND
006aaa485
Fig 5.
Application diagram: USB 2.0
Circuit board layout and protection device placement Circuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT) and surge transients. The following guidelines are recommended: 1. Place the PRTR5V0U2F and the PRTR5V0U2K as close to the input terminal or connector as possible. 2. The path length between the PRTR5V0U2F or the PRTR5V0U2K and the protected line should be minimized. 3. Keep parallel signal paths to a minimum. 4. Avoid running protected conductors in parallel with unprotected conductors. 5. Minimize all Printed-Circuit Board (PCB) conductive loops including power and ground loops. 6. Minimize the length of the transient return path to ground. 7. Avoid using shared transient return paths to a common ground point. 8. Ground planes should be used whenever possible. For multilayer PCBs, use ground vias.
PRTR5V0U2F_PRTR5V0U2K_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 19 February 2009
7 of 12
NXP Semiconductors
PRTR5V0U2F; PRTR5V0U2K
Ultra low capacitance double rail-to-rail ESD protection
8. Package outline
1.05 0.95 0.6
3 4
0.50 max 0.04 max 0.25 0.17 0.35
3
1.05 0.95 0.55
0.5 max 0.04 max
4
0.5 1.5 1.4 0.5
1 6 2 5
1.05 0.95 0.35
2
5
0.20 0.12
1
6
0.40 0.32 Dimensions in mm
0.35 0.27 04-07-22
0.40 0.32 Dimensions in mm
0.35 0.27 07-05-15
Fig 6.
Package outline PRTR5V0U2F (SOT886)
Fig 7.
Package outline PRTR5V0U2K (SOT891)
9. Packing information
Table 10. Packing methods The indicated -xxx are the last three digits of the 12NC ordering code.[1] Type number Package Description 4 mm pitch, 8 mm tape and reel; T1 4 mm pitch, 8 mm tape and reel; T4 PRTR5V0U2K SOT891
[1] [2] [3]
[2] [3]
Packing quantity 5000 -115 -132 -132
PRTR5V0U2F SOT886
4 mm pitch, 8 mm tape and reel
For further information and the availability of packing methods, see Section 13. T1: normal taping T4: 90 rotated reverse taping
PRTR5V0U2F_PRTR5V0U2K_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 19 February 2009
8 of 12
NXP Semiconductors
PRTR5V0U2F; PRTR5V0U2K
Ultra low capacitance double rail-to-rail ESD protection
10. Soldering
1.250 0.675
0.370 (6x) 0.500 1.700 0.500 0.270 (6x)
solder resist solder paste = solderland occupied area Dimensions in mm
0.325 (6x)
0.425 (6x)
sot886_fr
Reflow soldering is the only recommended soldering method.
Fig 8.
Reflow soldering footprint PRTR5V0U2F (SOT886)
1.05
0.5 (6x) 1.4 0.7
0.6 (6x)
solder resist solder land plus solder paste occupied area Dimensions in mm
0.15 (6x) 0.25 (6x)
0.35
sot891_fr
Reflow soldering is the only recommended soldering method.
Fig 9.
Reflow soldering footprint PRTR5V0U2K (SOT891)
PRTR5V0U2F_PRTR5V0U2K_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 19 February 2009
9 of 12
NXP Semiconductors
PRTR5V0U2F; PRTR5V0U2K
Ultra low capacitance double rail-to-rail ESD protection
11. Revision history
Table 11. Revision history Release date Data sheet status Product data sheet Product data sheet Change notice Supersedes PRTR5V0U2F_PRTR5V0U2K_1 Document ID Modifications:
PRTR5V0U2F_PRTR5V0U2K_2 20090219
*
Table 3 "Pinning": graphic symbol amended
PRTR5V0U2F_PRTR5V0U2K_1 20081106
PRTR5V0U2F_PRTR5V0U2K_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 19 February 2009
10 of 12
NXP Semiconductors
PRTR5V0U2F; PRTR5V0U2K
Ultra low capacitance double rail-to-rail ESD protection
12. Legal information
12.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
12.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. ESD protection devices -- These products are only intended for protection against ElectroStatic Discharge (ESD) pulses and are not intended for any other usage including, without limitation, voltage regulation applications. NXP Semiconductors accepts no liability for use in such applications and therefore such use is at the customer's own risk.
12.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk.
12.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
13. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
PRTR5V0U2F_PRTR5V0U2K_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 19 February 2009
11 of 12
NXP Semiconductors
PRTR5V0U2F; PRTR5V0U2K
Ultra low capacitance double rail-to-rail ESD protection
14. Contents
1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 10 11 12 12.1 12.2 12.3 12.4 13 14 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Application information. . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 Packing information. . . . . . . . . . . . . . . . . . . . . . 8 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Contact information. . . . . . . . . . . . . . . . . . . . . 11 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 19 February 2009 Document identifier: PRTR5V0U2F_PRTR5V0U2K_2

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